Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version
Thu Sep 28 09:06:57 2017
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Design: touch_top
Constraint file:
Report level: verbose report, limited to 3 items per constraint
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================================================================================
Constraint: create_clock -period 1000.000000 -name clk8 [get_nets key_num_data_10__N_21]
0 items scored, 0 timing errors detected.
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================================================================================
Constraint: create_clock -period 1000.000000 -name clk7 [get_nets clk_200khz]
0 items scored, 0 timing errors detected.
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Constraint: create_clock -period 1000.000000 -name clk6 [get_nets key_num_data_10__N_5]
0 items scored, 0 timing errors detected.
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Constraint: create_clock -period 1000.000000 -name clk5 [get_nets key_num_data_10__N_7]
0 items scored, 0 timing errors detected.
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Constraint: create_clock -period 1000.000000 -name clk4 [get_nets key_num_data_10__N_9]
0 items scored, 0 timing errors detected.
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Constraint: create_clock -period 1000.000000 -name clk3 [get_nets key_num_data_10__N_11]
0 items scored, 0 timing errors detected.
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Constraint: create_clock -period 1000.000000 -name clk2 [get_nets key_num_data_10__N_15]
0 items scored, 0 timing errors detected.
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================================================================================
Constraint: create_clock -period 1000.000000 -name clk1 [get_nets clk_in_c]
866 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 988.440ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3IX CK \cap1298_i2c_u3/cnt_200khz_1153__i2 (from clk_in_c +)
Destination: FD1P3JX SP \cap1298_i2c_u3/read_num_i0_i2 (to clk_in_c +)
Delay: 11.275ns (25.8% logic, 74.2% route), 6 logic levels.
Constraint Details:
11.275ns data_path \cap1298_i2c_u3/cnt_200khz_1153__i2 to \cap1298_i2c_u3/read_num_i0_i2 meets
1000.000ns delay constraint less
0.285ns LCE_S requirement (totaling 999.715ns) by 988.440ns
Path Details: \cap1298_i2c_u3/cnt_200khz_1153__i2 to \cap1298_i2c_u3/read_num_i0_i2
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \cap1298_i2c_u3/cnt_200khz_1153__i2 (from clk_in_c)
Route 2 e 1.198 \cap1298_i2c_u3/cnt_200khz[2]
LUT4 --- 0.493 B to Z \cap1298_i2c_u3/i1241_3_lut
Route 1 e 0.941 \cap1298_i2c_u3/n6_adj_281
LUT4 --- 0.493 A to Z \cap1298_i2c_u3/i3_4_lut_adj_20
Route 19 e 1.825 cnt_200khz_5__N_136
LUT4 --- 0.493 B to Z i290_2_lut_rep_97
Route 10 e 1.604 n7038
LUT4 --- 0.493 B to Z \cap1298_i2c_u3/i1_3_lut_rep_90_4_lut
Route 8 e 1.540 \cap1298_i2c_u3/n7031
LUT4 --- 0.493 B to Z \cap1298_i2c_u3/i1_3_lut_4_lut_4_lut_adj_47
Route 3 e 1.258 \cap1298_i2c_u3/clk_in_c_enable_37
--------
11.275 (25.8% logic, 74.2% route), 6 logic levels.
Passed: The following path meets requirements by 988.440ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3IX CK \cap1298_i2c_u3/cnt_200khz_1153__i2 (from clk_in_c +)
Destination: FD1P3JX SP \cap1298_i2c_u3/read_num_i0_i1 (to clk_in_c +)
Delay: 11.275ns (25.8% logic, 74.2% route), 6 logic levels.
Constraint Details:
11.275ns data_path \cap1298_i2c_u3/cnt_200khz_1153__i2 to \cap1298_i2c_u3/read_num_i0_i1 meets
1000.000ns delay constraint less
0.285ns LCE_S requirement (totaling 999.715ns) by 988.440ns
Path Details: \cap1298_i2c_u3/cnt_200khz_1153__i2 to \cap1298_i2c_u3/read_num_i0_i1
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \cap1298_i2c_u3/cnt_200khz_1153__i2 (from clk_in_c)
Route 2 e 1.198 \cap1298_i2c_u3/cnt_200khz[2]
LUT4 --- 0.493 B to Z \cap1298_i2c_u3/i1241_3_lut
Route 1 e 0.941 \cap1298_i2c_u3/n6_adj_281
LUT4 --- 0.493 A to Z \cap1298_i2c_u3/i3_4_lut_adj_20
Route 19 e 1.825 cnt_200khz_5__N_136
LUT4 --- 0.493 B to Z i290_2_lut_rep_97
Route 10 e 1.604 n7038
LUT4 --- 0.493 B to Z \cap1298_i2c_u3/i1_3_lut_rep_90_4_lut
Route 8 e 1.540 \cap1298_i2c_u3/n7031
LUT4 --- 0.493 B to Z \cap1298_i2c_u3/i1_3_lut_4_lut_4_lut_adj_47
Route 3 e 1.258 \cap1298_i2c_u3/clk_in_c_enable_37
--------
11.275 (25.8% logic, 74.2% route), 6 logic levels.
Passed: The following path meets requirements by 988.440ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1S3IX CK \cap1298_i2c_u3/cnt_200khz_1153__i2 (from clk_in_c +)
Destination: FD1P3JX SP \cap1298_i2c_u3/read_num_i0_i0 (to clk_in_c +)
Delay: 11.275ns (25.8% logic, 74.2% route), 6 logic levels.
Constraint Details:
11.275ns data_path \cap1298_i2c_u3/cnt_200khz_1153__i2 to \cap1298_i2c_u3/read_num_i0_i0 meets
1000.000ns delay constraint less
0.285ns LCE_S requirement (totaling 999.715ns) by 988.440ns
Path Details: \cap1298_i2c_u3/cnt_200khz_1153__i2 to \cap1298_i2c_u3/read_num_i0_i0
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \cap1298_i2c_u3/cnt_200khz_1153__i2 (from clk_in_c)
Route 2 e 1.198 \cap1298_i2c_u3/cnt_200khz[2]
LUT4 --- 0.493 B to Z \cap1298_i2c_u3/i1241_3_lut
Route 1 e 0.941 \cap1298_i2c_u3/n6_adj_281
LUT4 --- 0.493 A to Z \cap1298_i2c_u3/i3_4_lut_adj_20
Route 19 e 1.825 cnt_200khz_5__N_136
LUT4 --- 0.493 B to Z i290_2_lut_rep_97
Route 10 e 1.604 n7038
LUT4 --- 0.493 B to Z \cap1298_i2c_u3/i1_3_lut_rep_90_4_lut
Route 8 e 1.540 \cap1298_i2c_u3/n7031
LUT4 --- 0.493 B to Z \cap1298_i2c_u3/i1_3_lut_4_lut_4_lut_adj_47
Route 3 e 1.258 \cap1298_i2c_u3/clk_in_c_enable_37
--------
11.275 (25.8% logic, 74.2% route), 6 logic levels.
Report: 11.560 ns is the maximum delay for this constraint.
================================================================================
Constraint: create_clock -period 1000.000000 -name clk0 [get_nets key_num_data_10__N_19]
0 items scored, 0 timing errors detected.
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Timing Report Summary
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Constraint | Constraint| Actual|Levels
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| | |
create_clock -period 1000.000000 -name | | |
clk8 [get_nets key_num_data_10__N_21] | -| -| 0
| | |
create_clock -period 1000.000000 -name | | |
clk7 [get_nets clk_200khz] | -| -| 0
| | |
create_clock -period 1000.000000 -name | | |
clk6 [get_nets key_num_data_10__N_5] | -| -| 0
| | |
create_clock -period 1000.000000 -name | | |
clk5 [get_nets key_num_data_10__N_7] | -| -| 0
| | |
create_clock -period 1000.000000 -name | | |
clk4 [get_nets key_num_data_10__N_9] | -| -| 0
| | |
create_clock -period 1000.000000 -name | | |
clk3 [get_nets key_num_data_10__N_11] | -| -| 0
| | |
create_clock -period 1000.000000 -name | | |
clk2 [get_nets key_num_data_10__N_15] | -| -| 0
| | |
create_clock -period 1000.000000 -name | | |
clk1 [get_nets clk_in_c] | 1000.000 ns| 11.560 ns| 6
| | |
create_clock -period 1000.000000 -name | | |
clk0 [get_nets key_num_data_10__N_19] | -| -| 0
| | |
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All constraints were met.
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 2140 paths, 321 nets, and 1027 connections (77.1% coverage)
Peak memory: 66154496 bytes, TRCE: 1916928 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs